Integrated semiconductor memories such as flash memories have a storage capacity that can be increased, inter alia, by increasing the number of bits stored per memory cell. Nitride programmable read only memory (NROM) cells can store two bits per cell and are based on charge-trapping in a nitride layer of an ONO (oxide-nitride-oxide) gate dielectric. In order to store two bits per cell, charge is localized in two regions of the nitride layer of each cell and the charge stored in each region can be manipulated independently.
FIG. 7 shows a schematic cross-sectional view of an NROM cell 19. Arranged on top of a semiconductor substrate 1 is a charge-trapping element 5 and a gate stack 20 formed of a polysilicon layer 6, a tungsten silicide layer 7 and a cap nitride layer 8. Nitride spacers 10 are formed on both sidewalls of the charge-trapping element 5 and of the gate stack 20. A drain region 12 and a source region 13 of the memory cell 19 are also shown together with their respective contacts 14. The memory cells 19 in a memory are isolated from each other by shallow trench isolations (STI) 15.
The polysilicon layer 6 and the tungsten silicide (WSiX) layer 7 form the gate electrode 26 of the memory cell 19, which is connected by the word line for addressing the memory cell 19. As tungsten silicide has a significantly lower specific electrical resistivity than polysilicon, the electrical resistance of the word lines is reduced. Reducing the resistivity of the word line is especially important in large high-speed memories with long word lines.
The charge-trapping element 5 consists of a bottom oxide (SiO2) layer 2, a nitride (Si3N4) layer 3 and a top oxide (SiO2) layer 4 and is also known as an ONO structure. When a memory cell 19 is programmed by applying proper biases on the word line, the contacts 14 of drain region 12 and the source region 13, hot electrons are generated between the drain 12 and source 13 region and injected into the nitride layer 3 where the electrons are trapped.
The cap nitride layer 8 on top of the tungsten silicide layer 7 is used as a hard mask for etching the gate stack 20. For producing the nitride spacers 10, a conformal nitride layer is deposited on the sidewalls of the gate stack 20 and is then etched anisotropically in a direction perpendicular to the surface of the semiconductor substrate 1. The nitride spacers 10 are used for forming self-aligned contacts 14 for contacting the source region 13 and the drain region 12. They are also used for masking the regions of the source and drain implants.
NROM cells 19 with nitride spacers 10 made from silicon nitride (Si3N4) show poor electrical properties such as reduced charge retention after cycling tests.